Before Qimonda’s unfortunate demise last year, they delivered an impressive paper at IEDM  describing a “buried wordline” (BwL). Memory chip supplier Qimonda says it is about to begin commercial production of DRAM chips using its new “Buried Wordline” technology. Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce.
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The semiconductor device of claim 1wherein the lower buried word line includes polysilicon.
However, this is merely illustrative, and thus, the gate electrode layer and the buried word line are not limited to these materials. The semiconductor device of claim 1wherein the gate insulating layer is a thermal oxide layer. Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong.
The forming of the buried word line may comprise forming the lower buried word line in the lower region of the gate electrode layer, and forming the upper buried word line in the upper region of the gate electrode layer. However, this is merely illustrative and thus, the gate electrode layer and the buried word line are not limited to this recessed feature.
Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments and intermediate structures. Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same.
In example embodiments, the upper buried word line may include a silicide. Materials used to form the gate electrode layer and the buried word line will now be bburied in detail below.
The upper buried word line may comprise a silicide. Recessed gate structures including blocking members, methods of forming the same, semiconductor devices having the recessed gate structures and methods of forming the semiconductor devices. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The upper buried word line may be formed of a silicide e.
Example embodiments also provide a method of fabricating a semiconductor device having the buried word line structure as described above. Such technique is well known to those skilled in the art and thus, the detailed description thereof is omitted. Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same. The buried word line may be formed using a chemical vapor deposition, a physical vapor deposition PVDor an atomic layer deposition ALD method.
The capping layer may be formed of an insulating material e.
In example embodiments, the lower buried word line may include polysilicon. Like reference numerals refer to like elements throughout. As such, the degradation of the oxide layer, which may be caused by the formation of bueied titanium nitride layer, may be reduced or prevented. Accordingly, when the gate electrode layer includes polysilicon and is formed to a thickness of about 5 nm, wrodline atomic layer deposition may be carried out using the Si 3 H 8 gas.
6F2 buried wordline DRAM cell for 40nm and beyond – Semantic Scholar
Non-volatile semiconductor memory device having vertical transistors with the floating and control gates in a trench and fabrication method therefor. In example embodiments, forming of the buried word line may include forming a word line layer on the substrate so as to bury the trench, polishing the word line layer using chemical dordline polishing CMP and an etch-back method which uses a dry etch to expose the surface of the substrate, and recessing the polished word line layer into the substrate.
This was a marked change vuried their earlier technology, as until this point all of their product had been based on planar wordline structure with trench-style storage capacitors sunk into the die substrate. A gate insulating layer 16 is disposed on the bottom surface and the inner surface of the trench The buried word line may be formed by forming a word line layer on the substrate so as to bury the trench In example embodiments, the gate electrode layer may include polysilicon which may be formed using the atomic layer deposition method in which Si 3 H 8 may be used as a silicon source gas.
The semiconductor device of claim 1wherein the upper buried word line includes at least one of tungsten Waluminum AlCopper Cumolybdenum Motitanium Titantalum Taworeline ruthenium Ru. In general, when thinly forming a polysilicon layer using an atomic layer deposition method, SiH 4 gas or Si 2 H 6 gas may be used as the silicon source gas. Reference will now be made in detail to example embodiments, examples of which are illustrated in the accompanying drawings.
Accordingly, all such modifications are intended to be included within the scope of the claims.
In addition, the diffusion length may be shorter in comparison to the buried word line being formed only of silicide. As described above, the electrical resistance of the word line of the worrdline word line composed of the lower buried word line and the wirdline buried word line may be lower when the upper buried word line includes silicide and metal material.
The semiconductor device of claim 1wherein the gate electrode layer has a thickness within a range of about 1 to about 10 nm.
However, chlorine ions worfline TiCl 4 are diffused into the oxide layers and silicon channels, thereby forming traps in the oxide layers.
In addition, in the semiconductor device according to example embodiments, the gate electrode may be formed of a different material from that of the word line. In example embodiments, the trench may be formed to have a width within wordlnie range of about 10 to about nm. The forming of the upper buried word line may comprise forming a second word line layer on the substrate so as to bury the trench in which the lower buried word line is formed, polishing the second word line layer using chemical mechanical polishing and an etch back method which uses dry etch to expose the surface of the substrate, and recessing the polished second word line layer into wordljne substrate to form the upper buried word line.
In example embodiments, the gate electrode layer worsline be formed using a chemical vapor deposition CVD or an atomic layer deposition ALD method. The upper buried word line may be formed by forming a second word line layer not shown on the substrate so as to bury the trench including the lower buried word line It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
‘Buried Wordline’ DRAM becomes reality | Electronics News
In example embodiments, forming the buried word line may include forming a lower buried word line in a lower region of the gate electrode layer and forming an upper buried word line in an upper region of the gate electrode layer, the upper buried word line being formed of a material different from that of the lower buried word line. In example embodiments, the buried word line may be formed of any one selected from the group consisting of tungsten Waluminum Alcupper Cumolybdenum Motitanium Titantalum Taand ruthenium Ruor a combination thereof.
And they are in volume production, we have also found them in a point and shoot camera. Semiconductor wotdline and manufacturing method to avoid the problem of hammering column.